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 2. Formulate a verification plan, design and develop a verification platform, and develop test-related patterns (SV, C, Assembly, etc.); 

3. Proficient in SystemVerilog and Verilog HDL; 

4. Be proficient in various verification methods (CRV, direct pattern, CDC, Lint, etc.); 

5. Be proficient in scripting languages, such as Python, Perl or Tcl; 

6. Be familiar with the ASIC front-end design process and have relevant experience in RTL development; 

7. Have relevant experience in Design Verification, be familiar with UVM, and have more than 3 years of recent development experience; 

8. Experience in C/C++ is preferred; 

9. Demonstrate a strong sense of teamwork;

10. Be able to work effectively under pressure.