1. Proficient in Synopsys DC and PT, with more than 3 years of recent development experience;
2. Proficiency in Verilog HDL language;
3. Be familiar with SystemVerilog language;
4. Be familiar with EDA tools such as SpyGlass,nLint, and Perl/Shell/Tcl scripts;
5. Be proficient in VCS, ModelSim, QuestaSim and other simulation tools;
6. Be familiar with back-end EDA tools and back-end design processes, and be able to seamlessly communicate with back-end designers;
7. Demonstrate a strong sense of teamwork;
8. Be able to work effectively under pressure.
Zhejiang Public Network Security File No. 33010802012598